The invention relates to mounting multiple semiconductor dies in a package.
A typical semiconductor device starts with a single die that is sawed from a silicon wafer. Circuitry is formed on the die by a series of deposition, masking, diffusion, etching, and implanting steps. The back of the die is bare. The die is attached to the leadframe by an adhesive layer that can also serve to electrically insulate the die from the leadframe. The die is then electrically connected to the leadframe by wirebonding the lead fingers of the leadframe to a bonding pads disposed around the periphery of the die (conventional configuration), or down the center of the die in a lead-on-chip (LOC configuration). After wirebonding, the die and the leadframe are encapsulated in a molded plastic package that is hermetically sealed to protect the die from moisture and physical stress. The lead fingers extend outside the plastic package to form leads that are folded down the side of the plastic package.
Various methods have been developed to increase package density. For example, U.S. Pat. No. 5,012,323, having the same assignee as the present application, discloses a semiconductor package incorporating a pair of conventional semiconductor dies (a first die mounted over a second die) on a single leadframe. The bonding pads on a conventional die are located on its periphery. To enable the bonding pads of the second die to be wirebonded to the leadframe, the rectangular surface area of the first die (mounted over the second die) is shown as being smaller than that of the second die.